Incremental placement optimization (gate sizing + buffering + cell relocation)

You inherit a deliberately weak template for an industrial-style EDA problem: incremental placement optimization beyond detailed placement. Given a placed netlist, your method must improve its PPA (timing / power / wirelength) by simultaneously relocating cells, sizing gates (incl. VT swaps), and inserting buffers / inverter pairs — while keeping the placement legal and the netlist functionally equivalent. The shipped template only copies the seed placement through unchanged (a valid but zero-improvement submission). Going weak→strong is the task. Your submission is re-run on sealed, different hidden designs for scoring; the score is higher-is-better.

Hard Constraints

• Submit scripts (setup_environment.sh + run.sh), not precomputed answers — the grader re-runs them on hidden designs it never showed you. Do not key on visible design names.
• setup_environment.sh runs first (install/prepare any tools you need). run.sh is then invoked from /app/methods/main/ as:

bash ./run.sh <design_name> <TNS_weight α> <power_weight β> <WL_weight γ>

and must produce, directly under /app/methods/main/: - <design_name>.sol.def — a self-contained DEF of your final placement + netlist transforms. - <design_name>.sol.changelist — ECO commands (may be empty), processed top→bottom: - size_cell <cellName> <libCellName> - insert_buffer {load pins} <buffer lib cell> <new buffer name> <new net name> - insert_buffer -inverter_pairs {load pins} <inv lib cell> {new inv names} {new nets}

• Legality (enforced, illegal → score 0): all cells on valid placement sites, no overlaps; fixed IO ports and fixed macros/cells must not move; the netlist must stay functionally equivalent (buffer/inverter-pair insertion only); the .sol.def must be consistent with applying the changelist to the seed DEF.

What You Have

• The design's input files under /app/methods/main/testcases/<design>/: gate-level Verilog, seed DEF, SDC, LEF, Bookshelf (.nodes/.nets/.pl/.scl/.aux), SPEF, and cell/macro metadata. The shared ASAP7 library is at /app/methods/main/testcases/ASAP7/. Do not modify anything under testcases/.
• Visible designs to develop on: aes, ariane, des, pci_bridge32. The hidden designs used for scoring are different circuits in the same format.
• The editable template /app/methods/main/ — this is what gets graded. run.sh currently just copies the seed DEF to <design>.sol.def with an empty changelist (zero improvement). Improve it in place. The runtime provides python3 and openroad.

How It Is Judged

After your run, the grader re-runs your setup_environment.sh once, then your run.sh <design> 1.0 1.0 1.0 on each hidden design, and scores each output with OpenROAD:

S = 1000·P − 50·D − 30·R
P = α·TNS_impr + β·Power_impr + γ·WL_impr      (improvement ratios over the seed)
D = average per-cell Manhattan displacement (normalized)     R = runtime (normalized)

Higher S is better (more PPA improvement, less disruption, faster). The reported metric is the mean S over the hidden designs; illegal on any hidden design earns no credit.

Common Pitfalls

• Moving cells aggressively for PPA and blowing the displacement penalty (−50·D), or producing overlaps / off-site cells that fail legality → score 0.
• Sizing/buffering that breaks functional equivalence, or a .sol.def inconsistent with the changelist.
• Optimizing only the visible designs — hidden designs have different critical paths and scales.
• Treating design names as signal: run.sh must be deterministic and design-name-independent.